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ver1.0 / november . 2013 1 / 14 rm s20 6 1 eb 68 e a w - 160 0 data sheet ddr3 sdram 2 40 pin registered dimm b ased on e lpida 4 gb b - die 78 - ball fbga with lead - free (rohs compliant) ramaxel technology reserves the right to change products or specifications without notice. ? 2013 ramaxel technology co., ltd. all rights reserved.
ver1.0 / november . 2013 2 / 14 rm s20 6 1 eb 68 e a w - 160 0 r evision h istory revision no. history draft date remark 1.0 initial release november , 201 3
ver1.0 / november . 2013 3 / 14 rm s20 6 1 eb 68 e a w - 160 0 f eatures package: 2 40 - pin d ual - in - line ddr3 memory module ( r dimm) dansity: 8 gb organization: 1024 mb* 72 , 2 rank power supply: vdd = 1.5 v 0.075v d ata rates: 1600mbps(max.) backward compatible to 1333mbps/1066 m bps 8 independent internal banks bi - directional differential data strobe (dqs, dqs#) differential clock inputs (ck,ck#) commands entered on each rising ck edg e eight - bit pre - fetch architecture dqs edge - aligned with data for reads dqs center - aligned with data for writes dll to align dq and dqs transitions with ck data mask (dm) for masking write data b urst lengths (bl): 8 and 4 with burst chop(bc) zq calibration for dq drive and odt on - die termination (odt) serial presence detect (spd) with eeprom operating case temperature range: tc = 0 ~ 95 average refresh period 7.8us at 0 ~ 85 ; 3.9us at 85 ~ 95 asynchronous rese t lead - free (rohs compliant) for contact pads, electrolytic gold plating ordering information part number density organization component composition number of rank g old plating thickness(min.) rms2061eb68eaw - 1600 8 gb 1024 m* 72 512 m x 8 ( edj4208bbbg - gn - f ) * 18 2 0. 76 um detailed information for detailed electrical specifications and further information, ple ase refer to the component ddr3 sdram datasheet edj4208bbbg - gn - f . key parameters speed ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 unit 7 - 7 - 7 9 - 9 - 9 11 - 11 - 11 tck(min) 1.875 1.5 1.25 ns cas latency 5,6,7,8 5,6,7,8,9,10 5,6,7,8,9,10,11 tck trcd(min) 13.125 13. 5 13.75 ns trp(min) 13.125 13.5 13.75 ns tras(min) 37.5 36 35 ns trc(min) 50.625 49.5 48.75 ns address configuration organization row address column address bank address auto precharge 512 * 8 ( 4 gb ) based module a0 - a1 5 a0 - a9 ba0 - ba2 a10/ap
ver1.0 / november . 2013 4 / 14 rm s20 6 1 eb 68 e a w - 160 0 module type: s :240pin ddr3 registered dimm max speed: 1600: 1600m bps pcb number ramaxel module ecc: 1: with ecc dram package: w : w bga dram vendor: e :elpida module density: a : 8 gb dram die revision: (refer to dram manufacturer) power supply: e : 1.5v dram density: 68 : 4gb ( 512m * 8 b) p art n umber r m s 2 0 6 1 e b 68 e a w C 1600
ver1.0 / november . 2013 5 / 14 rm s20 6 1 eb 68 e a w - 160 0 p in assignments pin front pin back pin front pin back pin front pin back pin front pin back 1 vrefdq 121 vss 31 dq25 151 vss 61 a3 181 a1 91 dq41 211 vss 2 vss 122 dq4 32 vss 152 dm 3 / tdqs 12 5 62 vdd 182 vdd 92 vss 212 dm 5 / tdqs1 4 3 dq0 123 dq5 33 dqs $ $ $ $ $ $ 3 153 n c / tdqs $ $ $ $ $ $ $ 12 5 63 ck1 / nc 3 183 vdd 93 dqs $ $ $ $ $ $ 5 213 nc/ tdqs $ $ $ $ $ $ $ 14 4 dq1 124 vss 34 dqs3 154 vss 64 ck $ $ $ $ 1 / nc 3 184 ck0 94 dqs5 214 vss 5 vss 125 dm0/ tdqs9 5 35 vss 155 dq30 65 vdd 185 ck $ $ $ $ 0 95 vss 215 dq46 6 dqs $ $ $ $ $ $ 0 126 n c / tdqs $ $ $ $ $ $ $ 9 5 36 dq26 156 dq31 66 vdd 186 vdd 96 dq42 216 dq47 7 dqs0 127 vss 37 dq27 157 vss 67 vrefca 187 event $ $ $ $ $ $ $ $ $ 97 dq43 217 vss 8 vss 128 dq6 38 vss 158 nc 68 nc 188 a0 98 vss 218 dq52 9 dq2 129 dq7 39 nc 159 nc 69 vdd 189 vdd 99 dq48 219 dq53 10 dq3 130 vss 40 nc 160 vss 70 a10/ap 190 ba1 100 dq49 220 vss 11 vss 131 dq12 41 vss 161 dm 8 / tdqs 17 5 71 ba0 191 vdd 101 vss 221 dm 6 / tdqs1 5 5 12 dq8 132 dq13 42 dqs $ $ $ $ $ $ 8 162 n c / tdqs $ $ $ $ $ $ $ 17 5 72 vdd 192 ras $ $ $ $ $ 102 dqs $ $ $ $ $ $ 6 222 nc/ tdqs $ $ $ $ $ $ $ 15 5 13 dq9 133 vss 43 dqs8 163 vss 73 we $ $ $ $ $ 193 s % 0 103 dqs6 223 vss 14 vss 134 dm 1 / tdqs 10 5 44 vss 164 nc 74 cas $ $ $ $ $ 194 vdd 104 vss 224 dq54 15 dqs $ $ $ $ $ $ 1 135 n c / tdqs $ $ $ $ $ $ $ 10 5 45 nc 165 nc 75 vdd 195 odt0 105 dq50 225 dq55 16 dqs1 136 vss 46 nc 166 vss 76 s $ 1 / nc 2 196 a13 106 dq51 226 vss 17 vss 137 dq14 47 vss 167 nc, test 4 77 odt1 / nc 2 197 vdd 107 vss 227 dq60 18 dq10 138 dq15 48 nc 168 reset $ $ $ $ $ $ $ $ $ 78 vdd 198 s % 3 108 dq56 228 dq61 19 dq11 139 vss 49 nc 169 cke 1 / nc 2 79 nc 199 vss 109 dq57 229 vss 20 vss 140 dq20 50 cke0 170 vdd 80 vss 200 dq36 110 vss 230 dm 7 / tdqs1 6 5 21 dq16 141 dq21 51 vdd 171 a15 81 dq32 201 dq37 111 dqs $ $ $ $ $ $ 7 231 nc/ tdqs $ $ $ $ $ $ $ 16 5 22 dq17 142 vss 52 ba2 172 a14 82 dq33 202 vss 112 dqs7 232 vss 23 vss 143 dm 2 / tdqs 11 5 53 nc 173 vdd 83 vss 203 dm 4 / tdqs1 3 5 113 vss 233 dq62 24 dqs $ $ $ $ $ $ 2 144 n c / tdqs $ $ $ $ $ $ $ 11 5 54 vdd 174 a12 84 dqs $ $ $ $ $ $ 4 204 nc / tdqs $ $ $ $ $ $ $ 13 5 114 dq58 234 dq63 25 dqs2 145 vss 55 a11 175 a9 85 dqs4 205 dqs5 115 dq59 235 vss 26 vss 146 dq22 56 a7 176 vdd 86 vss 206 dq38 116 vss 236 vddspd 27 dq18 147 dq23 57 vdd 177 a8 84 dq34 207 dq39 117 sa0 237 sa1 28 dq19 148 vss 58 a5 178 a6 88 dq35 208 vss 118 scl 238 sda 29 vss 149 dq28 59 a4 179 vdd 89 vss 209 dq44 119 sa2 239 vss 30 dq24 150 dq29 60 vdd 180 a3 90 dq40 210 dq45 120 vtt 240 vtt notes 1. nc = no connect, nu = not useable. 2. s $ 1, odt1,cke1: used for dual - rank dimms; nc on single - rank dimms 3. ck1,nc and ck $ $ $ $ 1 ,nc : used for dual - rank dimms; not used on single - rank dimms, but terminated 4. test used by memory bus analysis tools (unused on memory dimms) 5 .dm[0:8] connected to dm on x8 drams , udm or ldm on x16 udimm drams , dm8 is not used on x64 udimms ; nc, tdqs[0:8] and tdqs $ $ $ $ $ $ $ [ 0 : 8 ] are not used on udimms.
ver1.0 / november . 2013 6 / 14 rm s20 6 1 eb 68 e a w - 160 0 pin functional d escription symbol type polarity function ck0/ ck 0 ck1/ ck 1 input cross point ck and ck are differential clock inputs. all the ddr3 sdram add/ctrl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is referenced to the crossing of ck and ck (both directions of crossing). cke[0:1] input active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, or the self refresh mode. s [0:1] input active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. this signal provides for external rank selection on systems with multiple ranks. ras , cas , we input active low ras , cas , and we (along with s ) define the command being entered. odt[0:1] input active high when high, termination resistance is enabled for all dq, dqs_t, dqs_c and dm pins, assuming this function is enabled on the dram. dm[0:8] input active high dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loadin g. tdqs[ 9 : 17 ], tdqs [ 9 : 17 ] output tdqs is enabled/disabled via the load mode command to the extended mode register (emr). when tdqs is enabled, dm is disabled and tdqs and tdqs# provide termination resistance; otherwise, tdqs# are no function. dqs[0:8] dqs [0:8] i/o cross point data strobe for input and output data. for raw cards using x16 organized drams, pins dq0 C dq7 are asso - ciated with the ldqs and ldqs pins and pins dq8 C dq15 are associated with udqs and udqs pins. ba[0:2] input - selects which sdram bank of eight is activated. a0 - a15 input - during a bank activate command cycle, address input defines the row address (ra0 C ra15).during a read or write command cycle, address input defines the column address. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be precharged. if ap is low, auto - precharge is disabled. during a precharge command cycle, ap is used in con junction with ba0, ba1, ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. a12( bc ) is sampled during read and write commands to determine if burst chop (on - the - fly) will be performed (high, no burst chop; low, burst chopped). dq[0:63] cb0 - cb7 i/o - data and check bit input/output pins. vdd, vss supply - power and ground for the ddr3 sdram input buffers, and core logic. vdd and vddq pins are tied to vdd/vddq planes on these modules. vddq supply - power supply for the ddr3 sdram output buffers to provide improved noise immunity. for all current ddr3 unbuffered dimm designs, vddq shares the same power plane as vdd pins. vddspd supply - power supply for spd eeprom. this supply is separate from the vdd/vddq power plane. eeprom supply is operable from 3.0v to 3.6v vrefdq supply - reference voltage for i/o inputs. vrefca supply - reference voltage for command/address inputs. sda i/o - this bidirectional pin is used to transfer data into or out of the spd eeprom. an external resistor may be connected from the sda bus line to vddspd to act as a pullup on the system board scl input - this signal is used to clock data into and out of the spd eeprom. an external resistor may be connected from the scl bus time to vddspd to act as a pullup on the system board. sa[0:2] input - these signals are tied at the system planar to either vss or vddspd to configure the serial spd eeprom address range. event output active low this signal indicates that a thermal event has been detected in the thermal sensing device. the system should guarantee the electrical level requirement is met for the event pin on the ts/spd part reset input active low the reset pin is connected to the reset pin on each dram. when low, all drams are set to a known state.
ver1.0 / november . 2013 7 / 14 rm s20 6 1 eb 68 e a w - 160 0 b lock d iagram raw card l 0 (x72 dimm, populated as two physical ranks of x 8 ddr3 sdrams ) notes: 1. dq-to-i/o wiring may be changed within a byte. 2. unless otherwise noted, resistor values are 15 ? 5%. 3. zq resistors are 240 ?????? for all other resistor values refer to the appropriate wiring diagram. v ss d0-d17 d0-d17 v dd d0-d17 vrefdq v ddspd serial pd vrefca v tt d0-d17 d0-d17 cb[7:0] dqs8_t dqs8_c dm8/dqs17_t dqs17_c d8 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d17 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] dq[31:24] dqs3_t dqs3_c dm3/dqs12_t dqs12_c d3 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d12 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] dq[23:16] dqs2_t dqs2_c dm2/dqs11_t dqs11_c d2 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d11 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] dq[15:8] dqs1_t dqs1_c dm1/dqs10_t dqs10_c d1 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[0:n]/ba[n:0] d10 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[0:n]/ba[n:0] dq[7:0] dqs0_t dqs0_c dm0/dqs9_t dqs9_c d0 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d9 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] rs0a_n rcasa_n rrasa_n rwea_n pck0a_c pck0a_t rcke0a rodt0a a[n:0]a /ba[n:0]a vtt dq[39:32] dqs4_t dqs4_c dm4/dqs13_t dqs13_c d4 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d13 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] dq[47:40] dqs5_t dqs5_c dm5/dqs14_t dqs14_c d5 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d14 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] dq[55:48] dqs6_t dqs6_c dm6/dqs15_t dqs15_c d6 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d15 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] dq[63:56] dqs7_t dqs7_c dm7/dqs16_t dqs16_c d7 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[n:0]/ba[n:0] d16 cs_n dqs_t dqs_c tdqs_t tdqs_c dq [7:0] cas_n ras_n we_n ck_c ck_t cke odt a[0:n]/ba[n:0] rs0b_n rcasb_n rrasb_n rweb_n pck0b_c pck0b_t rcke0b rodt0b a[n:0]b /ba[n:0]b vtt rs1a_c pck1a_c pck1a_t rcke1a rodt1a rs1b_n pck1b_c pck1b_t rcke1b rodt1b zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq a0 serial pd a1 a2 sa0 sa1 sda scl wp sa2 option 2 serial pd, no thermal sensor a0 integrated thermal sensor in spd a1 a2 sa0 sa1 sda scl event _n sa2 event _n option 1 serial pd w/ integrated thermal sensor
ver1.0 / november . 2013 8 / 14 rm s20 6 1 eb 68 e a w - 160 0 electrical specifications all voltages are referenced to vss (gnd). a bsolute m aximum dc r ating symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 ~ 1.975 v 1 vddq voltage on vddq pin relative to vss - 0.4 ~ 1.975 v 1 vin, vout voltage on any pin relative to vss - 0.4 ~ 1.975 v 1 tstg storage temperature - 55 ~ +100 1,2 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jesd51 - 2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6 x vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. m odule temperature condition operating temperature condition parameter symbol rating unit not es operating case temperature tc 0 to +95 1,2,3 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 to 85 under all operating conditions. 3. some applications require operation of the dram in the extended temperature range between 85 and 95 case temperature. full sp ecifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9s. (this double refres h requirement may not apply for some dev ices.) b) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self - refresh mode with extended temperature range capability (mr2 bit [a6, a7] = [0, 1]) or enable the optional auto self - refr esh mode (mr2 bit [a6, a7] = [1, 0]).
ver1.0 / november . 2013 9 / 14 rm s20 6 1 eb 68 e a w - 160 0 dc/ac o perating c ondition recommended dc operating conditions - ddr3 (1.5v) operation symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.5 1.575 v 1,2,3 vddq supply voltage for output 1.425 1.5 1.575 v 1,2,3 vrefca(dc) input reference voltage for address, command inputs 0.49*vdd - 0.51*vdd v 4,5, vrefdq(dc) input reference voltage for dq, dm inputs 0.49*vdd - 0.51*vdd v 4,5, notes: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than 1% vdd (for reference: approx 15 mv). 4 . for reference: appro x. vdd/2 15 mv.
ver1.0 / november . 2013 10 / 14 rm s20 6 1 eb 68 e a w - 160 0 idd s pecifications and conditions data rate (mbps) 1600 1333 1 066 parameter symbol max. max. max. unit notes operating current (act - pre) (another rank in idd2p1) idd0 900 855 7 65 ma operating current (act - pre) (another rank in idd3n) idd0 1080 1035 945 ma operating current (act - read - pre) (another rank in idd2p1) idd1 1845 1665 1485 ma operating current (act - read - pre) (another rank in idd3n) idd1 1350 1170 1080 ma precharge power - down standby idd2p 0 360 360 360 ma slow pd exit idd2p 1 630 630 540 ma fast pd exit precharge standby current idd2n 810 810 810 ma precharge standby odt current idd2nt 810 810 810 ma precharge quiet standby current idd2q 810 810 720 ma active power - down current (always fast exit) idd3p 702 666 666 ma active standby current idd3n 990 990 900 ma operating current (burst read operating) (another rank in idd2p1) idd4r 1440 1305 1125 ma operating current (burst read operating) (another rank in idd3n) idd4r 1575 1440 1305 ma operating current (burst write operating) (another rank in idd2p1) idd4w 2655 23625 2655 ma operating current (burst write operating) (another rank in idd3n) idd4w 2295 2205 2070 ma burst refresh current (another rank in idd2p1) idd5b 504 486 486 ma burst refresh current (another rank in idd3n) idd5b 495 495 2400 ma all bank interleave read current (another rank in idd2p1) idd7 1323 1188 1053 ma all bank interleave read current (another rank in idd3n) idd7 1395 1260 1125 ma reset low current idd8 306 306 306 ma parameter symbol max. unit notes self - refresh current normal temperature range idd6 396 ma self - refresh current extended temperature range idd6et 450 ma auto self - refresh current (optional) idd6tc - ma self - refresh current (tc = 0c to +85c, v vdd = 1.5 v 0.075v ) dc characteristics 1 (tc = 0c to +85c, vdd = 1.5 v 0.075v , vss = 0v)
ver1.0 / november . 2013 11 / 14 rm s20 6 1 eb 68 e a w - 160 0 spd matrix byte no. function described function support hex 0 number of serial pd bytes written/ spd device size / crc coverage 176/256/0 - 116 92 1 spd revision version 1. 1 11 2 key byte / dram device type ddr3 sdram 0b 3 key byte / module type rdimm 01 4 sdram density and banks 8 banks,4gb 04 5 sdram addressing 16 row 10 col 21 6 module nominal voltage, vdd 1. 5v 00 7 module organization 2ranks x8 09 8 module memory bus width 72bits/ecc 0b 9 fine timebase (ftb) dividend/divisor 2.5 ps 52 10 medium timebase (mtb) dividend 0.125ns 01 11 medium timebase (mtb) divisor 08 12 sdram minimum cycle time (tckmin) ddr3 1600 0a 13 reserved reserved 00 14 cas latencies supported, lsb 11,10,9,8,7,6,5, fe 15 cas latencies supported, msb - 00 16 minimum cas latency time (taamin) 13.125ns 69 17 minimum write recovery time (twrmin) 15ns 78 18 minimum ras# to cas# delay time (trcdmin) 13.125ns 69 19 minimum row active to row active delay time (trrdmin) 6ns 30 20 minimum row precharge delay time (trpmin) 13.125ns 69 21 upper nibbles for tras and trc refer to byte22,23 11 22 minimum active to precharge delay time (trasmin), lsb 35ns 18 23 minimum active to active/refresh delay time (trcmin), lsb 48.125ns 81 24 minimum refresh recovery delay time (trfcmin), lsb 260ns 20 25 minimum refresh recovery delay time (trfcmin), msb 260ns 08 26 minimum internal write to read command delay time (twtrmin) 7.5ns 3c 27 minimum internal read to precharge command delay time (trtpmin) 7.5ns 3c 28 upper nibble for tfaw 30ns 00 29 minimum four activate window delay time (tfawmin) 30ns f0 30 sdram optional features dll - off,rzq/7,6 83 31 sdram thermal and refresh options p asr,2x at 85 - 95 , 0 - 95 81 32 module thermal sensor incorporated 80 33 sdram device type standard 00 3 4 - 59 reserved reserved 00 60 module nominal height 18.75 04 61 module maximun thickness f:1 - 2mm, b:1 - 2mm 11 62 reference raw card used raw card: l1 0a 63 1 row,1 register 05 64 rdimm thermal heat spreader solution not incorporated 00 65 register manufacturer id code, lsb montage 86 dimm module attributes
ver1.0 / november . 2013 12 / 14 rm s20 6 1 eb 68 e a w - 160 0 66 register manufacturer id code, msb 32 67 register revision number 10 68 register type 00 69 rc1 (ms nibble) / rc0 (ls nibble) 00 70 rc3 (ms nibble) / rc2 (ls nibble) - drive strength,command/address 50 71 rc5 (ms nibble) / rc4 (ls nibble) - drive strength,control and clock 00 72 rc7 (ms nibble) / rc6 (ls nibble) - reserved for register vendor specific modes 00 73 rc9 (ms nibble) / rc8 (ls nibble) - reserved 00 74 rc11 (ms nibble) / rc10 (ls nibble) - reserved 00 75 rc13 (ms nibble) / rc12 (ls nibble) - reserved 00 76 rc15 (ms nibble) / rc14 (ls nibble) - reserved 00 77 - 116 reserved 00 117 module id: module manufacturer's jedec id code ramaxel 04 118 module id: module manufacturer's jedec id code 43 119 module id: module manufacturing location shenzhen 01 120 - 121 module id: module manufacturing date 00 122 - 125 module id: module serial number 00 126 cyclical redundancy code(crc) 07 127 cyclical redundancy code(crc) 4e 128 - 145 module part number r 52 129 m 4d 130 s 53 131 2 32 132 0 30 133 6 36 134 1 31 135 e 45 136 b 42 137 6 36 138 8 38 139 e 45 140 a 41 141 w 57 142 1 31 143 6 36 144 0 30 145 0 30 146 module revision code a 41 147 module revision code 00 148 dram manufacturer's jedec id code, lsb e lpida 02 149 dram manufacturer's jedec id code, msb e lpida fe 150 - 175 manufacturer's specific data 00 176 - 255 open for customer use 00
ver1.0 / november . 2013 13 / 14 rm s20 6 1 eb 68 e a w - 160 0 d imensions unit: mm * note: tolerances on all dimensions 0.15 unless otherwise specified . register clock driver spd/ts 1.27 4.0 max 18.10 12.60 133.35 18.75 raw card k front side back
ver1.0 / november . 2013 14 / 14 rm s20 6 1 eb 68 e a w - 160 0 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stresson these components to prevent damaging them.in particular, do not push module cover or drop the modules in order to protect from mechanical defect s, which would be electrical defects. when re - packing memory modules, be sure the modules are not touching each other.modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. notes for cmos devices 1) precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos de vices operation. steps must be taken to stop generation of static electricity as much as pos sible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti - static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2) handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to th e input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull - u p or pull - down circuitry. each unused pin should be connected to vdd or gnd with a resistor, if it is considered to have a possibility of being an output pi n. the unused pins must be handled in accordance with the related specifications. 3) status before ini tialization of mos devices power - on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power - on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after pow er - on for mos devices having reset function.

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